Case: 20-2222 Document: 63 Page: 1 Filed: 02/04/2022
United States Court of Appeals
for the Federal Circuit
______________________
CALIFORNIA INSTITUTE OF TECHNOLOGY,
Plaintiff-Appellee
v.
BROADCOM LIMITED, NKA BROADCOM INC.,
BROADCOM CORPORATION, AVAGO
TECHNOLOGIES LIMITED, NKA AVAGO
TECHNOLOGIES INTERNATIONAL SALES PTE.
LIMITED, APPLE INC.,
Defendants-Appellants
______________________
2020-2222, 2021-1527
______________________
Appeals from the United States District Court for the
Central District of California in No. 2:16-cv-03714-GW-
AGR, Judge George H. Wu.
______________________
Decided: February 4, 2022
______________________
KATHLEEN M. SULLIVAN, Quinn Emanuel Urquhart &
Sullivan, LLP, Los Angeles, CA, argued for plaintiff-appel-
lee. Also represented by JAMES R. ASPERGER; BRIAN P.
BIDDINGER, EDWARD J. DEFRANCO, New York, NY; TODD
MICHAEL BRIGGS, KEVIN P.B. JOHNSON, Redwood Shores,
CA; DEREK L. SHAFFER, Washington, DC; KEVIN
ALEXANDER SMITH, San Francisco, CA.
Case: 20-2222 Document: 63 Page: 2 Filed: 02/04/2022
2 THE CALIFORNIA INSTITUTE v. BROADCOM LIMITED
WILLIAM F. LEE, Wilmer Cutler Pickering Hale and
Dorr LLP, Boston, MA, argued for defendants-appellants.
Also represented by LAUREN B. FLETCHER, MADELEINE C.
LAUPHEIMER, JOSEPH J. MUELLER; STEVEN JARED HORN,
DAVID P. YIN, Washington, DC; MARK D. SELWYN, Palo
Alto, CA.
______________________
Before LOURIE, LINN, and DYK, Circuit Judges.
Opinion for the Court filed by Circuit Judge LINN.
Opinion concurring-in-part and dissenting-in-part filed by
Circuit Judge DYK.
LINN, Circuit Judge.
Broadcom Limited, Broadcom Corporation, and Avago
Technologies Ltd. (collectively “Broadcom”) and Apple Inc.
(“Apple”) appeal from the adverse decision of the District
Court for the Central District of California in an infringe-
ment suit filed by the California Institute of Technology
(“Caltech”) for infringement of its U.S. Patents No.
7,116,710 (“the ’710 patent”), No. 7,421,032 (“the ’032 pa-
tent”), and No. 7,916,781 (“the ’781 patent”).
Because the district court did not err in its construction
of the claim limitation “repeat” and because substantial ev-
idence supports the jury’s verdict of infringement of the as-
serted claims of the ’710 and ’032 patents, we affirm the
district court’s denial of JMOL on infringement thereof.
We also affirm the district court’s conclusion that claim 13
of the ’781 patent is patent-eligible but vacate the jury’s
verdict of infringement thereof because of the district
court’s failure to instruct the jury on the construction of the
claim term “variable number of subsets.” We thus remand
for a new trial on infringement of claim 13 of the ’781 pa-
tent. We further affirm the district court’s summary judg-
ment findings of no invalidity based on IPR estoppel and
its determination of no inequitable conduct. We affirm the
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THE CALIFORNIA INSTITUTE v. BROADCOM LIMITED 3
district court’s decision with respect to its jury instructions
on extraterritoriality. But because Caltech’s two-tier dam-
ages theory cannot be supported on this record, we vacate
the jury’s damages award and remand for a new trial on
damages.
BACKGROUND
I. The Caltech Patents
Caltech’s ’710 and ’032 patents disclose circuits that
generate and receive irregular repeat and accumulate
(“IRA”) codes, a type of error correction code designed to
improve the speed and reliability of data transmissions.
Wireless data transmissions are ordinarily susceptible to
corruption arising from noise or other forms of interfer-
ence. IRA codes help to identify and correct corruption af-
ter it occurs.
The encoding process begins with the processing of
data before it is transmitted. The data consists of infor-
mation bits in the form of 1’s and 0’s. The information bits
are input into an encoder, a device that generates code-
words comprised of parity bits and the original information
bits. Parity bits are appended at the end of a codeword.
Codewords are created in part by repeating information
bits in order to increase the transmission’s reliability.
When noise or other forms of interference introduce errors
into the codewords during transmission, the decoder iden-
tifies these errors and relies on the codeword’s redundant
incorporation of the original string of information bits to
correct and eliminate the errors.
Before Caltech’s patents, error correction codes had al-
ready incorporated repetition and irregular repetition.
These codes, however, were less than optimally efficient be-
cause they were either encoded or decoded in quadratic
time, which meant that the number of computations
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4 THE CALIFORNIA INSTITUTE v. BROADCOM LIMITED
required to correct a given number of bits far exceeded the
number of bits ultimately corrected.
In the ’710 and ’032 patents, the IRA codes are linear-
time encodable and decodable, rather than quadratic. ’710
patent, col. 2, ll. 6–7 (“The encoded data output from the
inner coder may be transmitted on a channel and decoded
in linear time.”); id. col. 2, l. 59 (“The inner coder 206 may
be a linear rate-1 coder.”); id. col. 3, ll. 25–26 (“An IRA code
is a linear code.”). Using a linear code means that the re-
lationship between the bits corrected and the computations
required is directly proportional. Minimizing the number
of calculations that an encoder or decoder must perform
permits smaller, more efficient chips with lower power re-
quirements.
The claimed improvement involves encoding the infor-
mation bits through a process of irregular repetition,
scrambling, summing, and accumulation. Repeating in-
putted information bits is necessary to increase the relia-
bility of data transmissions, and irregular repetition
minimizes the number of times that information bits are
repeated. Minimizing the number of times that an infor-
mation bit is repeated is crucial to the efficiency of the
claimed inventions because the repetitions impact the de-
vice’s coding rate or speed, as well as the code’s complexity.
The fewer repeated bits there are, the fewer number of
computations that an encoder must perform, which in turn
permits smaller circuits, decreased power requirements,
and decreased operating temperatures in devices incorpo-
rating the circuits.
The claims and accompanying specifications of the Cal-
tech patents make clear that each inputted information bit
must be repeated. The parties agree that every claim at
issue requires irregular repetition of information bits ei-
ther explicitly or via the court’s construction. This is so
even where the irregular repetition is not expressly
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THE CALIFORNIA INSTITUTE v. BROADCOM LIMITED 5
required by the claims. For example, the agreed-upon con-
struction of a Tanner graph in the ’032 patent requires that
“every message bit is repeated . . . .” J. App’x 33. Further-
more, the claims and accompanying specifications make
clear that each bit must be repeated irregularly, stating,
for example in the ’710 patent, “a fraction of the bits in the
block may be repeated two times, a fraction of bits may be
repeated three times, and the remainder of bits may be re-
peated four times.” ’710 patent, col. 2, ll. 53–58.
The ‘781 patent discloses and claims a method for cre-
ating codewords in which “information bits appear in a var-
iable number of subsets.” Before trial, Apple and
Broadcom sought summary judgment that claim 13 was
unpatentable under 35 U.S.C. § 101. After finding that the
claims were directed to a patent-eligible subject matter
(step 1 of Alice 1)—a method of performing error correction
and detection encoding with the requirement of irregular
repetition—the court declined to reach whether they con-
tained an inventive concept (step 2 of Alice). To support
patentability, Caltech argued that the “variable number of
subsets” language required irregular information bit repe-
tition. The district court agreed and adopted and relied on
Caltech’s interpretation to deny summary judgment of un-
patentability. No party on appeal challenges this claim in-
terpretation.
II. The Accused Products
Caltech alleged infringement by certain Broadcom Wi-
Fi chips and Apple products incorporating those chips, in-
cluding smartphones, tablets, and computers. The accused
Broadcom chips were developed and supplied to Apple pur-
suant to Master Development and Supply Agreements
1 Alice Corp. Pty. Ltd. v. CLS Bank Int’l, 573 U.S.
208 (2014).
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6 THE CALIFORNIA INSTITUTE v. BROADCOM LIMITED
negotiated and entered into in the United States. Caltech
specifically identified as infringing products two encode1·s
contained in the Broadcom chips-a Richardson-Urbanke
("RU") encoder and a low-area ("LA") encoder. In the ac-
cused encoders, incoming information bits are provided to
AND gates in the RU encoder or multiplexers in the LA
encodei·.
Throughout the ti·ial and on appeal, the parties treated
AND gates and multiplexers as functionally identical for
all relevant issues. It thus suffices to describe in detail the
RU encoder only. In the RU encoder, each information bit
is simultaneously fed as one input to 972 separate AND
gates. Each AND gate receives a second input-a "parity-
check" or "enable" bit of 0 or I-derived from a low-density
parity check matrix. This matrix is an anay of l 's and O's.
A low-density parity check matrix is one in which the num-
ber of l's in the matrix is significantly fewer than the num-
ber of O's.
In its brief, Broadcom presents the following table, us-
ing the example of the functioning of a single AND gate, to
show how outputs ai·e determined by the two inputs:
Input 1 Input 2 AND Gate
(Information Bit) (Parity-Check Bit) Output
0 0 0
0 1 0
1 0 0
1 1 1
For each AND gate, the output of the gate is 1 if both
inputs (the information bit and the parity-check bit) are l ;
otherwise, the output is 0. One consequence of this logic is
that if the parity-check bit is 1 (as shown in rows two and
four) , then the output is identical to the information-bit in-
put. If the parity-check bit is 0, the output is 0, regardless
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THE CALIFORNIA INSTITUTE v. BROADCOM LIMITED 7
of the value of the input (rows one and three). Throughout
trial, the parties referred to parity-check bits and enable
bits interchangeably. Parity-check bits determine the ac-
tion of the AND gates, which are open/on when the parity-
check bit is 1 and closed/off when the parity-check bit is 0.
Caltech sued Broadcom and Apple on May 26, 2016, al-
leging infringement under 35 U.S.C. § 271 by Broadcom
wireless chips and Apple products incorporating those
chips. Both defendants denied that any of the accused de-
vices infringed Caltech’s patents, and in turn asserted
counterclaims for declaratory judgment of non-infringe-
ment, invalidity under 35 U.S.C. §§ 101, 102, 103, and/or
112, and unenforceability due to inequitable conduct.
III. Pre-Trial Proceedings
Before trial, Apple filed multiple IPR petitions chal-
lenging the validity of the claims at issue, relying on vari-
ous prior art references. The Patent Trial and Appeal
Board (“PTAB” or “Board”) issued a number of written de-
cisions, which concluded that Apple failed to show the chal-
lenged claims were unpatentable as obvious. Before the
district court, Apple and Broadcom argued that the as-
serted claims would have been obvious over new combina-
tions of prior art not asserted in the IPR proceedings.
The district court granted summary judgment of no in-
validity, interpreting 35 U.S.C. § 315(e)(2) as precluding
parties from raising invalidity arguments at trial that they
reasonably could have raised in their IPR petitions. It also
denied the motion filed by Apple and Broadcom for sum-
mary judgment of invalidity under 35 U.S.C. § 101 for the
’781 patent. The district court granted Caltech’s summary
judgment motion as to inequitable conduct, finding no in-
equitable conduct with respect to Caltech’s failure to dis-
close Richardson99 during prosecution. The district court
reasoned that this prior art reference was not but-for ma-
terial to the PTO’s grant of Caltech’s patents.
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8 THE CALIFORNIA INSTITUTE v. BROADCOM LIMITED
The district court also conducted a Markman hearing
and initially construed the claim limitation “repeat.” That
construction is germane to all of the asserted claims. At
the conclusion of the Markman hearing, the district court
construed “repeat” to have its plain and ordinary meaning.
The district court noted that the repeated bits “are a con-
struct distinct from the original bits from which they are
created,” but that they need not be generated by storing
new copied bits in memory.
IV Trial Proceedings
A. Infringement of the ’710 and ’032 Patents
At trial, Caltech argued that the accused chips in-
fringed claims 20 and 22 of the ’710 patent and claims 11
and 18 of the ’032 patent. Both groups of claims explicitly
require irregular repetition; i.e., repetition of groups of in-
formation bits an irregular number of times. Claims 20
and 22 of the ’710 patent depend from claim 15, which
claims:
15. A coder comprising: a first coder having an in-
put configured to receive a stream of bits, said first
coder operative to repeat said stream of bits irreg-
ularly and scramble the repeated bits; and a second
coder operative to further encode bits output from
the first coder at a rate within 10% of one.
’710 patent, col. 8, ll. 1–6. Claims 11 and 18 of the ’032
patent cover devices for encoding and decoding pursuant to
a Tanner graph: 2
2 During claim construction, the parties agreed that
a Tanner graph is a visual representation of the “con-
straints that determine the parity bits” created by an IRA
code. J. App’x 33.
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THE CALIFORNIA INSTITUTE v. BROADCOM LIMITED 9
11. A device comprising: an encoder configured to
receive a collection of message bits and encode the
message bits to generate a collection of parity bits
in accordance with the following Tanner graph:
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\c} I
·~....•
•·····---r3\:
. . ...\:8L
c✓.